Title: Bluespec: Advanced Modeling, Design and Verification using High-Level Synthesis Speaker: Rishiyur Nikhil CTO, Bluespec, Inc. Date: Thursday, October 2nd. 10.30am Location: Galois, Inc., 421 SW 6th Ave. Suite 300, (3rd floor of the Commonwealth Building)

ABSTRACT:

Over the past few years, several projects in major companies have been adopting BSV (Bluespec SystemVerilog) as their next-generation tool of choice for IP design, modeling (for both architecture exploration and early software development), and verification enviroments.

The reason for choosing BSV is its unique combination of:

(1) excellent computation model for expressing complex concurrency and communication, based on atomic transactions and atomic transactional inter-module methods

(2) very high level of abstraction and parameterization (principally inspired by Haskell)

(3) full synthesizability, enabling execution on FPGAs, obtaining better performance (3 to 4 orders of magnitude) and scalability than software simulation at comparable levels of detail.

In this presentation, I will provide a brief technical overview of BSV (points 1-3 above), and describe several customer projects using BSV. I will also briefly contrast BSV with other approaches to High Level Synthesis (particularly those based on C/C++/SystemC).

BIOGRAPHY:

Rishiyur S. Nikhil is co-founder and CTO of Bluespec, Inc., which develops tools that dramatically improve correctness, productivity, reuse and maintainability in the design, modeling and verification of digital designs (ASICs and FPGAs). The core technologies consist of a language, BSV (Bluespec SystemVerilog), which enables very abstract source descriptions based on scalable atomic transactions and extreme parameterization, and tools for high-quality synthesis of BSV into RTL. Earlier, from 2000 to 2003, he led a team inside Sandburst Corp. (later acquired by Broadcom) developing Bluespec technology and contributing to 10Gb/s enterprise network chip models, designs and design tools.

From 1991 to 2000 he was at Cambridge Research Laboratory (DEC/Compaq), including one and a half years as Acting Director. From 1984 to 1991 he was a professor of Computer Science and Engineering at MIT. He has led research teams, published widely, and holds several patents in functional programming, dataflow and multithreaded architectures, parallel processing, compiling, and EDA. He is a member of ACM and IFIP WG 2.8 on Functional Programming, and a Senior Member of IEEE. He received his Ph.D. and M.S.E.E. in Computer and Information Sciences from the Univ. of Pennsylvania, and his B.Tech in EE from IIT Kanpur.

ABOUT THE GALOIS TECH TALKS:

Galois (http://galois.com) has been holding weekly technical seminars for several years on topics from functional programming, formal methods, compiler and language design, to cryptography, and operating system construction, with talks by many figures from the programming language and formal methods communities.

The talks are open and free. If you're planning to attend, dropping a note to [email protected] is appreciated, but not required. If you're interested in giving a talk, we're always looking for new speakers.

There are people who get really excited about building hardware and Open Source. There are a few holes in the stack, and as a community we can get started on fundamental tools that will make things easier for all of us. Some topics that came up in the session on Saturday.

The tools for programming FPGA's are all proprietary let's design an open source FPGA, most of the patents are running out soon.

There are open source 3d modeling tools, but will they tell you where the center of gravity of your amature rocket is? That's an important thing to know when it passes mach 1.

Radio is awesome.

Look for an "Art of Community" book, or a tshirt that says "free as in freedom" amongst the dorkbot crowd to find the discussion. Don't worry if you miss this meeting there isn't even a listserv up yet it's a meeting of convenience as many of the people from Saturday's discussion are going to be at DorkBot anyways.

An Introduction to Verilog Synthesis by Galen Seitz

This talk will introduce you to the joys and pitfalls of programmable logic design using Verilog. The focus will be on small designs that could conceivably be undertaken by hobbyists. While we could easily spend weeks on the subject, we will try to cram the following into an hour and a half or so:

• Overview of PALs, CPLDs, and FPGAs
• Why use programmable logic
• Verilog constructs for synthesis
• Synthesis workflow
• Simulation
• Guidelines for synthesis
• A demonstration

If your digital logic skills are a bit rusty, you may want to brush up on your understanding of logic gates and D flip-flops ahead of time. There are many sources of info on the net. Here are couple that may be useful:

http://www.cs.oberlin.edu/~jdonalds/210/lecture08.html http://www.cs.oberlin.edu/~jdonalds/210/lecture12.html

Many will break for the Lucky Lab on Hawthorne afterwards.

Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source IP blocks and SoCs, open source simulators, compilers, synthesis and physical implementation tools for both FPGA and ASIC.

Latch-Up aims to bring together the North American open source digital design community for an event in the mould of ORConf - the FOSSi Foundation’s annual European community conference. Like ORConf, Latch-Up will be will be free to attend and consist of a relaxed format of presentations and discussions throughout a weekend, with plenty of time for networking. A dinner on the Saturday evening will be arranged and all attendees are invited to attend.

These events go to the FOSSi Foundation's goal of lowering barriers of entry to the digital design field, whilst encouraging the open source development model and promoting open collaboration.

We recognise the keen interest in this area in the Americas and this year are putting effort into organizing an event which will encourage wider awareness amongst enthusiasts of the projects that we’ve been hearing about at ORConf since 2012.

The current status of the event is that we are finalizing venue details, which will be close to central Portland. We will update the page and make details known via social media as they emerge.