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  <div class="vevent h-event"> <h1 class="summary p-name">IEEE - The Impact of Resonant, Distributed, Frequency and Transmission Properties of Interconnects upon Nano-Scale VLSI Devices Reliability and Functionality</h1> <div class='date'><time class="dtstart dt-start" title="2010-03-31T18:00:00" datetime="2010-03-31T18:00:00">Wednesday, March 31, 2010 from 6</time>–<time class="dtend dt-end" title="2010-03-31T19:00:00" datetime="2010-03-31T19:00:00">7pm</time></div> <div class="location vcard p-location h-card"> <a class="url" href='http://calagator.org/venues/202391991'><span class='fn org p-name'>University of Portland, Shiley Hall, Room 124</span></a> <div class="adr p-adr h-adr"> <div class="street-address p-street-address">5000 N. Willamette Blvd.</div> <span class="locality p-locality">Portland</span> , <span class="region p-region">Oregon</span> <span class="postal-code p-postal-code">97203 </span> <div class="country-name p-country-name">US</div> (<a href='https://maps.google.com/maps?q=5000%20N.%20Willamette%20Blvd.,%20Portland%20Oregon%2097203%20%20US'>map</a>) </div> </div> <div class="description p-description"> <p>Title: The Impact of Resonant, Distributed, Frequency and Transmission Properties of Interconnects upon Nano-Scale VLSI Devices Reliability and Functionality Speaker: Pavel Livshits, Bar Ilan University, Israel When: Wednesday, March 31, 2010, 5:30 – 7:00pm Where: U Portland, Shiley Hall 124 Directions: See <a href="http://www.up.edu/about/default.aspx?cid%EF%BF%BD07&pid177">http://www.up.edu/about/default.aspx?cid�07&pid177</a> Food: Pizza and Soda RSVP: Requested - register at <a href="http://meetings.vtools.ieee.org/meeting_registration/register/1991">http://meetings.vtools.ieee.org/meeting_registration/register/1991</a></p> <p>Pavel Livshits from Bar Ilan University, Israel will present some of the findings of his doctoral research.</p> <p>Abstract: Rapid development of Systems-on-a-Chip (SoC) over the last decade has set tougher signal integrity requirements for on-die signal and power distribution networks. At the same time, only a very few experimental works have been conducted to study the properties of on-die interconnects constituting these networks. In this talk, results obtained within the framework of our experimental study on global interconnects, constructed as transmission lines, that carry out on-die global signaling and on interconnects constituting power supply and ground grids, are presented. In the study we employed VLSI engineering samples typical for 90 nm and 45 nm CMOS technology nodes. We found that local voltage fluctuations in power supply and ground grids, excited by on-die logic cell switching have a resonant-like form. This finding resolves the discussed in literature controversy over the need for considering parasitic inductance i.e., the on-die power grids should be described as an RLC circuit. We experimentally observed and confirmed by modeling that the active element (i.e., CMOS logic cell) influences the frequency properties of power supply and ground grids during its switching (as opposed to before or after switching). Thus, it was shown that frequency properties of both grids are inter-related via the interconnecting active elements. In our experimental study was found that the impedance matching between CMOS driver and a driven transmission line, and the Ohmic losses of on-die transmission lines, implemented by standard metal layers of modern technology nodes, play an important role in circuits’ performance. The study suggests that impedance mismatch results in excessive power consumption and signal integrity problems. The high Ohmic losses result in a significant distortion and Inter-Symbol Interference of already a few hundreds Mega-Hertz signals. Our study reveals that relatively low but repetitive voltage oscillations on on-die power supply and ground grids, excited by logic cells switching, may lead not only to logic faults, as it has been regarded, but also to an accumulated damage of VLSI MOSFETs. Thus, according to Berkley Reliability Tools models simulations they accelerate the device degradation due to three main wearout mechanisms, such as Time-Dependent Dielectric Breakdown, Negative Bias Temperature Instability and Hot Carrier Injection. The similar device damage, as the study shows, is caused by the impedance mismatch induced distortions of signals supplied to input of on-die CMOS logic cells.</p> <p>Speaker(s): Pavel Livshits,</p> <p>Agenda: Wednesday, March 31, 2010, 5:30 – 7:00pm</p> <p>Location: Room: 124 Bldg: Shiley Hall University of Portland 5000 N. Willamette Blvd. Portland 97203</p> </div> </div>