Change 4564

Time Attribute with previous and current values
Change #4564
2010-10-09
15:22:33

create Calagator::Event 1250459339 Oregon - EDS Lecturer: Transistor Nanotechnologies for High Performance-Power Efficient Logic Technologies Roll back

description nil → Co-sponsored by: CAS/CPMT and ED/MTT Chapters IEEE Oregon ED/MTT and CAS/CPMT Chapters Present IEEE EDS Distinguished Lecture Transistor Nanotechnologies for High Performance-Power Efficient Logic Technologies Speaker: Tahir Ghani, Intel Fellow, Logic Technology Development, Intel Corporation Date: Wednesday, October 27, 2010 Time: 6:30-9 pm Pizza and social at 6:30; talk at 7pm Location: PCC Willow Creek Center, Room 313; 241 SW Edgeway Drive (near SW 185th and Baseline Road), Beaverton, OR 97006 Directions: http://www.pcc.edu/about/locations/willow-creek/ SEATS LIMITED, please register below. Abstract: The scaling of CMOS technology dimensions has led to phenomenal growth in transistor density and performance during the last four decades. However, recently the industry has started to experience significant challenges in achieving historical transistor performance gains through traditional dimensional scaling. Intel has been at the forefront in addressing these challenges by successfully driving transistor innovations from research phase to mainstream CMOS manufacturing. Implementation of uniaxial strained-silicon transistors at the 90nm node and the “HiK+Metal Gate” transistors for the 45nm node are two excellent examples of major innovations by Intel which have demonstrated dramatic performance enhancement. After a general review of technology evolution trends, I will discuss how these specific innovations have enabled dramatic performance enhancement for the recent CMOS nodes and describe specific challenges which had to be overcome to expedite their implementation into mainstream CMOS manufacturing. In the second part of my talk, I will present how future innovations in device architecture, novel process modules and material systems have the potential to successfully address upcoming scaling challenges in a power-limited era. This talk will highlight a list of open fundamental challenges which need to be successfully addressed before these new innovations can be implemented into mainstream CMOS technology. Directions: PCC Willow Creek Center is accessible by car off 185th Avenue, and by MAX at the Willow Creek/SW 185th Ave stop. Speaker(s): Tahir Ghani, Intel Fellow, Agenda: 6:30 pm - Pizza and social 7:00 pm - Lecture Location: Room: Room 313 Bldg: PCC Willow Creek Center 241 SW Edgeway Drive (near SW 185th and Baseline Road) Beaverton 97006
end_time nil → 2010-10-27 20:30:00 -0700
id nil → 1250459339
source_id nil → 996334221
start_time nil → 2010-10-27 18:30:00 -0700
title nil → Oregon - EDS Lecturer: Transistor Nanotechnologies for High Performance-Power Efficient Logic Technologies
venue_id nil → 202392218