An Introduction to Verilog Synthesis by Galen Seitz

This talk will introduce you to the joys and pitfalls of programmable logic design using Verilog. The focus will be on small designs that could conceivably be undertaken by hobbyists. While we could easily spend weeks on the subject, we will try to cram the following into an hour and a half or so:

• Overview of PALs, CPLDs, and FPGAs
• Why use programmable logic
• Verilog constructs for synthesis
• Synthesis workflow
• Simulation
• Guidelines for synthesis
• A demonstration

If your digital logic skills are a bit rusty, you may want to brush up on your understanding of logic gates and D flip-flops ahead of time. There are many sources of info on the net. Here are couple that may be useful:

http://www.cs.oberlin.edu/~jdonalds/210/lecture08.html http://www.cs.oberlin.edu/~jdonalds/210/lecture12.html

Many will break for the Lucky Lab on Hawthorne afterwards.