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IEEE Oregon - USB 3.0 Workshop at OctoberBest 2010

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Tektronix Bldg 38
3025 SW Zworykin Avenue
Beaverton, Oregon 97077, US (map)

Description

IEEE OctoberBest Seminars
IEEE01: USB 3.0 Workshop
Speakers: Howard Heck, Jon Schenk, Dan Froelich, Intel



Date: Wednesday, October 6, 2010
Time: 9:00 AM – 11:45 AM
Location: Tektronix Conference Center, 13975 SW Karl Braun Drive Beaverton OR 97077
Cost: $75/$99 (See Registration Section for complete pricing info)
CEUs: 0.3 CEUs (3 PDH) awarded upon completion
“The IEEE has been approved as an Authorized Provider by the International Association for Continuing Education and Training (IACET). In obtaining this approval, the IEEE has demonstrated that it complies with the ANSI/IACET Standards which are widely recognized as standards of good practice internationally. As a result of their Authorized Provider membership status, IEEE is authorized to offer IACET CEUS for its programs that qualify under the ANSI/IACET Standards.” IACET CEU Provider #1255

This is a half-day technical seminar sponsored by the IEEE Oregon Section CPMT and CAS Joint Chapter.

Registration/check-in starts at 8:30 am, with the seminar starting promptly at 9:00.



This workshop will describe the specifications, technologies, and design and testing methodologies principles for 5 Gb/s SuperSpeed USB 3.0 signaling.



This workshop consists of these three Modules:

  • Electrical Specifications (a.k.a. Physical Layer) - Howard Heck
  • System and Device Design - Jon Schenk
  • Electrical Compliance Testing - Dan Froelich

Each module would be targeted for 45 minutes in length.



Workshop Description



**Module 1 - Electrical Specifications (a.k.a. Physical Layer) - Howard Heck



The Electrical Specification module will focus on the key features of the physical layer specification that make SuperSpeed operation possible. The material will include descriptions of the advancements in the cable performance characteristics, the use of equalization in the transceiver, and innovations in the jitter budgeting and testing methodologies that allow scaling of the interface to 5 Gb/s while remaining within the consumer electronics cost envelope.



**Module 2 - System and Device Design - Jon Schenk



The Design Guidelines module will describe the techniques recommended for the designers of transceivers, packages, devices, and host controllers boards. This will include layout rules for host PCB designs for notebook and desktop systems, stackup and layout guidelines for low cost SuperSpeed devices, and training methodologies for the high speed I/O transceivers.



**Module 3 - Electrical Compliance Testing - Dan Froelich



The Electrical Compliance Testing module will cover details of the electrical portion of the USB-IF compliance program for SuperSpeed USB signaling. We will describe transmitter compliance test and related signal analysis algorithms, and receiver jitter tolerance testing including calibration. Details of the set-up for the compliance tests including standard fixtures will also be covered. The session will also provide some background into how the various methods and algorithms were selected.



Intended audience: I/O circuit/package/board design and test engineers, though the material is intended to communicate to a general electronics audience.



Prerequisites: None.



Learning Objectives: Attendees will get an understanding of the key aspects of developing SuperSpeed products, in-depth knowledge of both design techniques and trade-offs and of the compliance testing requirements.



Registration:
The seminar will be held Wednesday, October 6 at the Tektronix Conference Center on the Tektronix Beaverton Campus, 14200 SW Karl Braun Drive, Beaverton, OR 97077. Registration/check-in starts at 8:30 AM, with the seminar starting promptly at 9:00. Refreshments will be provided. Lecture notes will provided to all attendees. In addition, 0.3 CEU’s (3 PDH) will be awarded upon completion of the seminar.



Registration Fee: IEEE $75; Other $99



NOTE: The registration fee includes one copy of the lecture notes, continental breakfast, morning break, and admission to OctoberBest exhibits. Keynotes are not included, and require separate registration. The organizing committee reserves the right to substitute speakers, restrict size, change venues, or to cancel the seminar. In the event the seminar is canceled by the organizing committee, registration fees only will be fully refunded. Individuals canceling their registration prior to September 29 will receive a full refund. No refunds will be made to individuals who cancel their registration after September 29. Substitute attendees accepted. Attendance is limited. Registration will be confirmed on a first come, first served basis.



Speakers:


Howard Heck
Howard Heck has 25 years experience working in the electronic packaging and signal integrity. Since joining Intel in 1995, he has focused on R&D of high speed inter-chip signaling solutions in technical and management roles for a number of products, including the Pentium® II/III/IV Frontside Bus, Direct RDRAM™, DDR II and Accelerated Graphics Port (AGP) interfaces. He currently leads development of the specifications and interconnect solutions for SuperSpeed USB 3.0 technology. From 1997 through 2009, he was an Adjunct Professor at the Oregon Graduate Institute, teaching High Speed Signal Integrity and Interconnect Design. He is an IEEE Senior Member, is co-author of Advanced Signal Integrity for High-Speed Digital Designs, a graduate level SI textbook published in 2009.



Jon Schenk
Jon Schenk graduated with a BSEE in 1982 from the University of Idaho. He worked at Intel from 1982 through 1991 starting out in Reliability Engineering then working into Design Evaluation and eventually Design Engineering on Multibus II board products. Jon worked for Tera Computer from 1991 through 1998 on the Multithreaded Architecture (MTA) I/O architecture and ASIC implementation. Since returning to Intel in 1998, Jon has worked as a Signal Integrity Engineer on various memory and high speed serial interfaces with the most recent being USB3.



Dan Froelich
Dan Froelich graduated with a BS. in Physics with honors and high distinction from Harvey Mudd College in 1996. He worked for National Instruments as an applications engineer and software developer for embedded system drivers until 2000 - when he joined Intel. At Intel Dan's first big project involved working on various aspects and providing overall technical leadership for Intel's contributions to the USB 2.0 compliance program. He has subsequently played similar roles for PCI Express 1.x, 2.0, 3.0, USB 3.0, Wireless USB, and Wimedia. Dan has also authored both protocol and electrical sections of the USB 3.0, Wireless USB, Wimedia MAC, and PCI Express 2.0 and 3.0 base and CEM specifications.



Contacts:
Howard Heck, Intel, [email protected]


Dan Froelich, Intel, [email protected]


Jon Schenk, Intel, [email protected]


Agenda: Schedule:

8:30 am – Registration and Refreshments
9:00 – 9:45 am – Module 1 - Electrical Specifications
9:50 – 10:35 am – Module 2 - System and Device Design
10:35 – 10:50 am –Break (approximate)
10:50 – 11:40 am – Module 3 -Electrical Compliance Testing
11:40 – 11:45 am – Wrap-up, CEU evaluations
11:45am – 1:00pm – OctoberBest 2010 Lunch Keynote (requires separate OctoberBest registration)

Location: Bldg: Tektronix Conference Center Building 38 13975 SW Karl Braun Drive Beaverton 97077

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