BEGIN:VCALENDAR PRODID;X-RICAL-TZSOURCE=TZINFO:-//Calagator//EN CALSCALE:GREGORIAN X-WR-CALNAME:Calagator METHOD:PUBLISH VERSION:2.0 BEGIN:VTIMEZONE TZID;X-RICAL-TZSOURCE=TZINFO:America/Los_Angeles BEGIN:DAYLIGHT DTSTART:20080309T020000 RDATE:20080309T020000 TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT END:DAYLIGHT END:VTIMEZONE BEGIN:VEVENT CREATED;VALUE=DATE-TIME:20081001T193211Z DTEND;TZID=America/Los_Angeles;VALUE=DATE-TIME:20081002T120000 DTSTART;TZID=America/Los_Angeles;VALUE=DATE-TIME:20081002T103000 DTSTAMP;VALUE=DATE-TIME:20081001T193211Z LAST-MODIFIED;VALUE=DATE-TIME:20081001T193211Z UID:http://calagator.org/events/1250455788 DESCRIPTION:Title: Bluespec: Advanced Modeling\, Design and Verifica tion using High-Level Synthesis \;\nSpeaker: Rishiyur Nikhil CTO\, Bluespec\, Inc. \;\nDate: Thursday\, October 2nd. 10.30am \ ;\nLocation: Galois\, Inc.\, 421 SW 6th Ave. Suite 300\, (3rd floor of the Commonwealth Building) \;\n \;\n \;\nABSTRACT: \;\n \;\nOver the past few years\, several projects in major companies have b een adopting BSV (Bluespec SystemVerilog) as their next-generation tool of choice for IP design\, modeling (for both architecture exploration an d early software development)\, and verification enviroments. \;\n 3\;\nThe reason for choosing BSV is its unique combination of: \;\n&# 13\;\n(1) excellent computation model for expressing complex concurrency and communication\, based on atomic transactions and atomic transaction al inter-module methods \;\n \;\n(2) very high level of abstractio n and parameterization (principally inspired by Haskell) \;\n \;\n (3) full synthesizability\, enabling execution on FPGAs\, obtaining bett er performance (3 to 4 orders of magnitude) and scalability than softwar e simulation at comparable levels of detail. \;\n \;\nIn this pres entation\, I will provide a brief technical overview of BSV (points 1-3 above)\, and describe several customer projects using BSV. I will also briefly contrast BSV with other approaches to High Level Synthesis (part icularly those based on C/C++/SystemC). \;\n \;\n \;\nBIOGRAPHY : \;\n \;\nRishiyur S. Nikhil is co-founder and CTO of Bluespec\, Inc.\, which develops tools that dramatically improve correctness\, prod uctivity\, reuse and maintainability in the design\, modeling and verifi cation of digital designs (ASICs and FPGAs). The core technologies cons ist of a language\, BSV (Bluespec SystemVerilog)\, which enables very ab stract source descriptions based on scalable atomic transactions and ext reme parameterization\, and tools for high-quality synthesis of BSV into RTL. Earlier\, from 2000 to 2003\, he led a team inside Sandburst Corp. (later acquired by Broadcom) developing Bluespec technology and contrib uting to 10Gb/s enterprise network chip models\, designs and design tool s. \;\n \;\nFrom 1991 to 2000 he was at Cambridge Research Laborat ory (DEC/Compaq)\, including one and a half years as Acting Director. F rom 1984 to 1991 he was a professor of Computer Science and Engineering at MIT. He has led research teams\, published widely\, and holds severa l patents in functional programming\, dataflow and multithreaded archite ctures\, parallel processing\, compiling\, and EDA. He is a member of A CM and IFIP WG 2.8 on Functional Programming\, and a Senior Member of IE EE. He received his Ph.D. and M.S.E.E. in Computer and Information Scie nces from the Univ. of Pennsylvania\, and his B.Tech in EE from IIT Kanp ur. \;\n \;\n \;\nABOUT THE GALOIS TECH TALKS: \;\n \;\nG alois (http://galois.com) has been holding weekly technical seminars for several years on topics from functional programming\, formal methods\, compiler and language design\, to cryptography\, and operating system co nstruction\, with talks by many figures from the programming language an d formal methods communities. \;\n \;\nThe talks are open and free . If you're planning to attend\, dropping a note to is appreciated\, bu t not required. If you're interested in giving a talk\, we're always loo king for new speakers.\n\nTags: galois\, technology\, functional program ming\, pdxfunc\, asic\, fpga\n\nImported from: http://calagator.org/even ts/1250455788 URL:http://galois.com SUMMARY:Galois Tech: Advanced Modeling\, Design and Verification using Hi gh-Level Synthesis LOCATION:Galois\, Inc: 421 SW 6th Ave. Suite 300\, Portland OR 97204 US SEQUENCE:0 END:VEVENT END:VCALENDAR