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CREATED;VALUE=DATE-TIME:20120503T233127Z
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UID:http://calagator.org/events/1250462357
DESCRIPTION:An Introduction to Verilog Synthesis by Galen Seitz\n\nThis t
 alk will introduce you to the joys and pitfalls of programmable logic de
 sign using Verilog.  The focus will be on small designs that could conce
 ivably be undertaken by hobbyists.  While we could easily spend weeks on
  the subject\, we will try to cram the following into an hour and a half
  or so:\n\n* Overview of PALs\, CPLDs\, and FPGAs\n* Why use programmabl
 e logic\n* Verilog constructs for synthesis\n* Synthesis workflow\n* Sim
 ulation\n* Guidelines for synthesis\n* A demonstration\n\nIf your digita
 l logic skills are a bit rusty\, you may want to brush up on your unders
 tanding of logic gates and D flip-flops ahead of time. There are *many* 
 sources of info on the net.  Here are couple that may be useful:\n\nhttp
 ://www.cs.oberlin.edu/~jdonalds/210/lecture08.html\nhttp://www.cs.oberli
 n.edu/~jdonalds/210/lecture12.html\n\nMany will break for the Lucky Lab 
 on Hawthorne afterwards.\n\nTags: linux\, fpga\, bsd\, Verilog\, EE\, El
 ectrical Engineering\n\nImported from: http://calagator.org/events/12504
 62357
URL:http://pdxlinux.org/
SUMMARY:PLUG Advanced Topics: Verilog Synthesis
LOCATION:Free Geek: 1731 SE 10th Avenue\, Portland OR 97214 US
SEQUENCE:1
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